From material to a switch

How can a voltage control a current path?

Operate a bounded long-channel nMOS teaching model and connect its inputs, regions and limitations.

A transistor connects material structure with controlled electrical behavior. Change the gate voltage in a simplified nMOS example and inspect the resulting drain current. The gate influences the channel through an electric field. The model is a useful learning tool whose output depends on its stated assumptions and parameter values.

Explore the model (optional)

EXPLORE THE MODEL

Control a teaching transistor

Separate layers to inspect their roles

INTERACTIVE 3DLayered schematic

Inside a silicon switchDrag to rotate · scroll or pinch to zoom

Turn slowlyInspect component

Silicon bodySource regionDrain regionChannelInsulating oxideGate electrode

Above the teaching threshold, a conducting channel can connect source and drain. Drain bias drives current; the gate controls the channel across an insulating layer.

What this representation means

Original idealized long-channel nMOS cutaway. Geometry, material colors, doping profiles and layer thicknesses are illustrative. Exploding the layers is a viewing aid, not a fabrication process. It omits leakage, short-channel effects and detailed electrostatics.

Gate bias: 1.8 V
Drain bias: 1.5 V
Teaching threshold: 1.0 V
Channel: Inversion in this model

Source: ocw.mit.edu ↗

B: filled green point. Markers identify the selected drain voltage and current; each curve spans the available drain voltages.

View sampled plot values

Current values

Drain voltage (V)	Drain current (mA)
0.000	0.00000
0.100	0.07500
0.200	0.14000
0.300	0.19500
0.400	0.24000
0.500	0.27500
0.600	0.30000
0.700	0.31500
0.800	0.32000
0.900	0.32000
1.000	0.32000
1.100	0.32000
1.200	0.32000
1.300	0.32000
1.400	0.32000
1.500	0.32000
1.600	0.32000
1.700	0.32000
1.800	0.32000
1.900	0.32000
2.000	0.32000
2.100	0.32000
2.200	0.32000
2.300	0.32000
2.400	0.32000
2.500	0.32000
2.600	0.32000
2.700	0.32000
2.800	0.32000
2.900	0.32000
3.000	0.32000
3.100	0.32000
3.200	0.32000
3.300	0.32000

Ideal long-channel nMOS teaching model, Vₜ = 1 V and k = 1 mA/V². No leakage, short-channel, temperature or manufacturing prediction.

Gate voltage1.8 V

Drain voltage1.5 V

TEACHING RELATIONSHIPIᴅ = k[(Vɢ−Vₜ)Vᴅ − Vᴅ²/2] or k(Vɢ−Vₜ)²/2

Drain current0.320 mA

Operating regionsaturation

Threshold1.0 V

The same gate and drain settings determine both the readout and the current–voltage curve. This is an ideal teaching device.

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HOW DO WE KNOW?

Evidence & limits

Reference science + bounded teaching model

What this interaction establishes

Operate a bounded long-channel nMOS teaching model and connect its inputs, regions and limitations.

Ideal long-channel nMOS teaching model, Vₜ = 1 V and k = 1 mA/V². No leakage, short-channel, temperature or manufacturing prediction.

Source bindings for this explanation

Start here

Sources: S01, S18, SRC-MOS.

Explore the science

For this long-channel teaching model, define overdrive VOV = VGS − VT. With nonnegative VDS, the model sets current to zero when VOV ≤ 0. For 0 ≤ VDS < VOV, ID = β(VOV·VDS − VDS²/2); for VDS ≥ VOV, ID = βVOV²/2. The gate controls the modeled channel state, while drain-to-source voltage participates in the current relation. Units and the selected β and threshold must stay visible.

Sources: S01, S18, SRC-MOS.

Go deeper

These equations compress device physics into an idealized gradual-channel account. They omit subthreshold leakage, channel-length modulation, velocity saturation, parasitic capacitance, temperature variation and many effects important in modern devices. The same inputs must drive the diagram, numerical readout and text summary. A region labeled saturation describes this model's current relation; it does not mean the device has maximum possible computation speed or that a real transistor draws exactly the predicted current.

Sources: S01, S18, SRC-MOS.

Limitations

The model is restricted to its stated long-channel nMOS assumptions and input domain. Zero below threshold is a simplification and omits real leakage. Outputs are not fabrication sign-off, production performance or switching-speed forecasts.

Sources: S01, S18, SRC-MOS.

Keep these boundaries in mind

The model is restricted to its stated long-channel nMOS assumptions and input domain.
Zero below threshold is a simplification and omits real leakage.
Outputs are not fabrication sign-off, production performance or switching-speed forecasts.

Inspect the references

Supplemental primary reference ↗Supplemental primary reference ↗

Scientific explanations with linked references. Model calculations retain their stated assumptions and limits.

Optional: check your understanding

MAKE THE CONNECTION YOUR OWN

Test your reasoning

Try freely. Saving progress is optional.

recognition

Which input directly controls the modeled gate-to-source bias?

A microscope zoom factorVGSThe number of scenes visited

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mechanism

In the stated model, what happens when VGS is at or below VT?

The material becomes a different elementThe output proves there is no leakage in any transistorThe model returns zero drain current under its cutoff approximation

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evidence

The simulated current agrees with its equation. What has been checked?

Internal consistency of the teaching calculation, not accuracy for every real deviceThe quality of an actual semiconductor waferThe speed of a complete AI system

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transfer

A modern transistor measurement differs from this long-channel model. What is a useful response?

Declare the measurement impossibleExamine the model assumptions and omitted effects before interpreting the discrepancyChange the units until the numbers look similar

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Small changes, different behavior Next: Inspect the manufactured world

EXPLORE THE MODEL

Control a teaching transistor

Separate layers to inspect their roles

INTERACTIVE 3DLayered schematic

Inside a silicon switchDrag to rotate · scroll or pinch to zoom

Turn slowlyInspect component

Silicon bodySource regionDrain regionChannelInsulating oxideGate electrode

Above the teaching threshold, a conducting channel can connect source and drain. Drain bias drives current; the gate controls the channel across an insulating layer.

What this representation means

Gate bias: 1.8 V
Drain bias: 1.5 V
Teaching threshold: 1.0 V
Channel: Inversion in this model

Source: ocw.mit.edu ↗

B: filled green point. Markers identify the selected drain voltage and current; each curve spans the available drain voltages.

View sampled plot values

Current values

Drain voltage (V)	Drain current (mA)
0.000	0.00000
0.100	0.07500
0.200	0.14000
0.300	0.19500
0.400	0.24000
0.500	0.27500
0.600	0.30000
0.700	0.31500
0.800	0.32000
0.900	0.32000
1.000	0.32000
1.100	0.32000
1.200	0.32000
1.300	0.32000
1.400	0.32000
1.500	0.32000
1.600	0.32000
1.700	0.32000
1.800	0.32000
1.900	0.32000
2.000	0.32000
2.100	0.32000
2.200	0.32000
2.300	0.32000
2.400	0.32000
2.500	0.32000
2.600	0.32000
2.700	0.32000
2.800	0.32000
2.900	0.32000
3.000	0.32000
3.100	0.32000
3.200	0.32000
3.300	0.32000

Ideal long-channel nMOS teaching model, Vₜ = 1 V and k = 1 mA/V². No leakage, short-channel, temperature or manufacturing prediction.

Gate voltage1.8 V

Drain voltage1.5 V

TEACHING RELATIONSHIPIᴅ = k[(Vɢ−Vₜ)Vᴅ − Vᴅ²/2] or k(Vɢ−Vₜ)²/2

Drain current0.320 mA

Operating regionsaturation

Threshold1.0 V

The same gate and drain settings determine both the readout and the current–voltage curve. This is an ideal teaching device.